CAT24C208
Table 5. D.C. OPERATING CHARACTERISTICS (V CC = 2.5 V to 5.5 V, unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
I CC
I SB
I LI
I LO
V IL
V IH
VHYS
V OL1
V CCL1
V CCL2
Power Supply Current
Standby Current (V CC = 5.0 V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Input Hysteresis
Output Low Voltage (V CC = 3 V)
Leakage DSP V CC to DDC V CC
Leakage DDC V CC to DSP V CC
f SCL = 100 KHz
V IN = GND or either DSP or DDC V CC
V IN = GND to either DSP or DDC V CC
V OUT = GND to either DSP or DDC V CC
I OL = 3 mA
? 1
V CC x 0.7
0.05
3
50
10
10
V CC x 0.3
V CC + 0.5
0.4
± 100
± 100
mA
m A
m A
m A
V
V
V
V
m A
m A
Table 6. A.C. CHARACTERISTICS (V CC = 2.5 V to 5.5 V, unless otherwise specified.)
Symbol
Parameter
Min
Max
Units
READ & WRITE CYCLE LIMITS
F SCL
T I (Note 6)
t AA
t BUF (Note 6)
t HD:STA
t LOW
t HIGH
t SU:STA
t HD:DAT
t SU:DAT
t R (Note 6)
t F (Note 6)
t SU:STO
t DH
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out and ACK Out
Time the Bus Must be Free Before a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1.3
0.6
1.3
0.6
0.6
0
100
0.6
100
400
100
0.9
300
300
kHz
ns
m s
m s
m s
m s
m s
m s
ns
ns
ns
ns
m s
ns
Table 7. POWER ? UP TIMING (Notes 6 and 7)
Symbol
t PUR
t PUW
Parameter
Power ? up to Read Operation
Power ? up to Write Operation
Min
Typ
Max
1
1
Units
ms
ms
6. This parameter is tested initially and after a design or process change that affects the parameter.
7. t PUR and t PUW are the delays required from the time V CC is stable until the specified operation can be initiated.
Table 8. WRITE CYCLE LIMITS
Symbol
t WR
Parameter
Write Cycle Time
Min
Typ
Max
5
Units
ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle.
During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond
to its slave address.
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